1. Field of the Invention
This invention relates to a pipelined multiple issue packet switch.
2. Description of Related Art
When computers are coupled together into networks for communication, it is known to couple networks together and to provide a switching device which is coupled to more than one network. The switching device receives packets from one network and retransmits those packets (possibly in another format) on another network. In general, it is desirable for the switching device to operate as quickly as possible.
However, there are several constraints under which the switching device must operate. First, packets may encapsulate differing protocols, and thus may differ significantly in length and in processing time. Second, when switching packets from one network to another, it is generally required that packets are re-transmitted in the same order as they arrive. Because of these two constraints, known switching device architectures are not able to take advantage of significant parallelism in switching packets.
It is also desirable to account ahead of time for future improvements in processing hardware, such as bandwidth and speed of a network interface, clock speed of a switching processor, and memory size of a packet buffer, so that the design of the switching device is flexible and scaleable with such improvements.
The following U.S. Patents may be pertinent:
U.S. Pat. No. 4,446,555 to Devault et al., xe2x80x9cTime Division Multiplex Switching Network For Multiservice Digital Networksxe2x80x9d;
U.S. Pat. No. 5,212,686 to Joy et al., xe2x80x9cAsynchronous Time Division Switching Arrangement and A Method of Operating Samexe2x80x9d;
U.S. Pat. No. 5,271,004 to Proctor et al., xe2x80x9cAsynchronous Transfer Mode Switching Arrangement Providing Broadcast Transmissionxe2x80x9d; and
U.S. Pat. No. 5,307,343 to Bostica et al., xe2x80x9cBasic Element for the Connection Network of A Fast Packet Switching Nodexe2x80x9d.
Accordingly, it would be advantageous to provide an improved architecture for a packet switch, which can make packet switching decisions responsive to link layer (ISO level 2) or protocol layer (ISO level 3) header information, which is capable of high speed operation at relatively low cost, and which is flexible and scaleable with future improvements in processing hardware.
The invention provides a pipelined multiple issue link layer or protocol layer packet switch, which processes packets independently and asynchronously, but reorders them into their original order, thus preserving the original incoming packet order. Each stage of the pipeline waits for the immediately previous stage to complete, thus causing the packet switch to be self-throttling and thus allowing differing protocols and features to use the same architecture, even if possibly requiring differing processing times. The multiple issue pipeline is scaleable to greater parallel issue of packets, and tunable to differing switch engine architectures, differing interface speeds and widths, and differing clock rates and buffer sizes.
In a preferred embodiment, the packet switch comprises a fetch stage, which fetches the packet header into one of a plurality of fetch caches, a switching stage comprising a plurality of switch engines, each of which independently and asychronously reads from corresponding fetch caches, makes switching decisions, and writes to a reorder memory, a reorder engine which reads from the reorder memory in the packets"" original order, and a post-processing stage, comprising a post-process queue and a post-process engine, which performs protocol-specific post-processing on the packets.